Method to Minimize the Clock Skew and Uniform Clock Distribution using Parallel Port in Pipe Line Based Multi Channel DMA Request Terminal for Frequency Measurement

This paper presents a new wide-range digital speed measurement method with jitter removal technique and using the direct memory access (DMA) terminal count register (TCR). Our work also supports a multi node interfacing from different measure ends. The multiple measure ends are interfaced with DMA channels through pipelines to improve hit ratio. Here hit ratio indicates the exact identification of encoder pulses without any fail or miss. But the conventional pipeline system is facing problems due to improper synchronization of clock pulses. This is a universal problem in all the digital systems mostly called jitter or skew. Here a new system is implemented in the path of the clock to remove or reduce the clock skew. The jitter is also introduced in the pipeline due to different clock paths to the parallel pipelines. While one pipeline access the encoder pulses the remaining pipelines remain in idle state as single clock pulse is used to fed encoder pulses. And it creates a big challenge if multiple clock pulses are given to individual pipeline systems. This can be overcome using parallel ports as clock signals. The DMA method is based on both pulses counting in the constant sampling time at terminal count stop pin of a DMA controller. The hardware configuration and algorithms for a microcontroller implementation are also presented. The proposed method is suitable in systems using microcontrollers with DMA controller and timers. Limitations and sources of errors are discussed in details. The DMA Terminal count register method is suitable for real-time speed control systems.